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product specification main office: nordic vlsi asa - vestre rosten 81, n-7075 tiller, norway - phone +4772898900 - fax +4772898989 revision: 3.0 page 1 of 11 august 31 st 2001 10-bit 20msps sampling analog-to-digital converter features 1.8v power supply snr typ 60db for ( f in = 10mhz) low power (15mw @ 1.8v and 20msps) frequency dependent biasing internal sample/hold differential input low input capacitance power down and sleep mode applications imaging test equipment computer scanners wireless communication powerline communication set top boxes video products general description the NAD1020-18 is a compact, high-speed, low power 10-bit monolithic analog-to- digital converter, implemented in a 0.18 m m single poly cmos process with mim capacitor option. the converter includes a high bandwidth sample and hold. using internal references, the full scale range is 0.75v. the full scale range can be set between 0.5v and 0.75v using external references. it operates from a single 1.8v supply. its low distortion and high dynamic range offers the performance needed for demanding imaging, multimedia, telecommunications and instrumentation applications. the bias current level for the adc is automatically adjusted based on the clock input frequency. hence, the power dissipation of the device is continuously minimised for the current operation frequency. quick reference data symbol parameter conditions min. typ. max. unit v dd supply voltage 1.6 1.8 2.0 v i dd supply current (20 msps) 8.3 ma p d power dissipation (10 msps) except digital output drivers 8mw p d power dissipation (20 msps) except digital output drivers 15 mw dnl differential nonlinearity f in =0.9991mhz 0.5 lsb inl integral nonlinearity f in =0.9991mhz 0.75 lsb f s conversion rate 20 mhz n resolution 10 bit table 1. quick reference data NAD1020-18
product specification NAD1020-18 10 bit 20 msps sampling adc ip main office: nordic vlsi asa - vestre rosten 81, n-7075 tiller, norway - phone +4772898900 - fax +4772898989 revision: 3.0 page 2 of 11 august 31 st 2001 general description (continued) the NAD1020-18 has a pipelined architecture - resulting in low input capacitance. digital error correction of the 9 most significant bits ensures good linearity for input frequencies approaching nyquist. the NAD1020-18 is compact. the core occupies less than 0.9mm 2 of die area in a standard single poly 0.18 m m cmos process. the fully differential architecture makes it insensitive to substrate noise. thus it is ideal as a mixed signal asic macro cell. block diagram figure 1. block diagram NAD1020-18 analog corr_log anclock bit<9:0> in_corr<17:0> ckbus<3:0> clock inn inp refp refn bias0 bias1 clockbuf extref ckcorr<1:0> ck0 ck0b ck2 ck2b vc m
product specification NAD1020-18 10 bit 20 msps sampling adc ip main office: nordic vlsi asa - vestre rosten 81, n-7075 tiller, norway - phone +4772898900 - fax +4772898989 revision: 3.0 page 3 of 11 august 31 st 2001 electrical specifications ( at t a =25 c, v dd = 1.8v, sampling rate = 20mhz, input frequency = 10mhz, differential input signal, 50% duty cycle clock unless otherwise noted ) symbol parameter (condition) test level min. typ. max. units dc accuracy dnl differential nonlinearity f in = 0.9991 mhz iv 0.5 lsb inl integral nonlinearity f in = 0.9991 mhz iv 0.75 lsb v os midscale offset 1 %fs cmrr common mode rejection ratio -59 db e g gain error 1 %fs dynamic performance snr signal to noise ratio (without harmonics) f in = 10 mhz iv 56 60 dbfs f in = 40 mhz iv 55 58.5 dbfs sinad signal to noise and distortion ratio f in = 10 mhz iv 59 dbfs sfdr spurious free dynamic range f in = 10 mhz iv 68 db f in = 40 mhz iv 57 db analog input v fsr input voltage range (differential) iv 0.75 v v cmi common mode input voltage iv 0.9 v c ina input capacitance (from each i nput to ground) 1.5 pf reference voltages v refni internal reference voltage on pin 10 iv 0.525 v v refpi internal reference voltage on pin 11 iv 1.275 v internal reference voltage drift 100 ppm/ c v refno negative input voltage iv 0.525 v v refpo positive input voltage iv 1.275 v v refp -v refn reference input voltage range 1) iv 0.75 v v cm common mode output voltage iv 0.9 v switching performance f s conversion rate iv 20 msps pipeline delay iv 6 clocks t ap aperture delay, ip v 0.9 ns t h output hold time, ip v 0.5 ns t d output delay time, ip v 2.5 ns t ap aperture delay, with bonding pad v 1.0 ns t h output hold time, with bonding pad v 1.0 ns t d output delay time, with bonding pad v 4.0 ns digital inputs v il logic 0 voltage iv 0.4 v v ih logic 1 voltage iv av dd -0.4 v i il logic 0 current (v i =v ss )iv 10 m a i ih logic 1 current (v i =v dd )iv 10 m a c ind input capacitance iv 5 pf (table continued on next page)
product specification NAD1020-18 10 bit 20 msps sampling adc ip main office: nordic vlsi asa - vestre rosten 81, n-7075 tiller, norway - phone +4772898900 - fax +4772898989 revision: 3.0 page 4 of 11 august 31 st 2001 digital outputs v ol logic 0 voltage (i = 2 ma) iv 0.2 0.4 v v oh logic 1 voltage (i = 2 ma) iv 85% ov dd 90% ov dd v power supply v dd supply voltage v 1.6 1.8 2.0 v i dd supply current (except digital output) iv ma v ss supply voltage gnd p d power dissipation (except digital output) (10 msps) iv 8 mw p d power dissipation (except digital output) (20 msps) iv 15 mw p d power dissipation (except digital output) power down mode 2) iv 45 w p d power dissipation (except digital output) sleep mode iv 655 w av dd - dv dd1 analog power C digital power pins -0.2 +0.2 v ov dd output driver supply voltage 1.6 1.8 2.0 v t ambient operating temperature -40 +85 c table 2. electrical specifications 1) seefigure5. 2) power down mode is only available for ip version of NAD1020-18. test levels test level i: 100% production tested at +25c test level ii: 100% production tested at +25c and sample tested at specified temperatures test level iii: sample tested only test level iv: parameter is guaranteed by design and characterization testing test level v: parameter is typical value only test level vi: 100% production tested at +25c. guaranteed by design and characterization testing for industrial temperature range absolute maximum ratings supply voltages av dd ............................- 0.2v to +2.2v dv dd1 ..................- 0.2v to v dd + 0.2v ov dd ...................- 0.2v to v dd + 0.2v input voltages analog in.......... - 0.2v to av dd + 0.2v digital in..............- 0.2v to v dd + 0.2v ref p ................. - 0.2v to av dd + 0.2v ref n ................. - 0.2v to av dd + 0.2v clock ...............- 0.2v to v dd + 0.2v temperatures operating temperature .-40 to +85 c storage temperature.. ... - 65 to +125 c note: stress above one or more of the limiting values may cause permanent damage to the device.
product specification NAD1020-18 10 bit 20 msps sampling adc ip main office: nordic vlsi asa - vestre rosten 81, n-7075 tiller, norway - phone +4772898900 - fax +4772898989 revision: 3.0 page 5 of 11 august 31 st 2001 pin functions pin name description inp inn differential input signal pins. common mode voltage: 0.9v refp refn reference input pins. bypass with 100nf capacitors close to the pins. see application information below. bias0, bias1 digital inputs for max. sampling rate programming. bias1=0, bias0=0: sleep mode (power save) bias1=0, bias0=1: - 12.5% bias bias1=1, bias0=0: +12.5% bias bias1=1, bias0=1: typ. bias the bias setting is automatically performed based on the clock input frequency. this function should be used only if another bias setting than typical must be used. clock clock input vcm common mode voltage output bit9 - bit0 digital outputs ( msb to lsb) or overrange. high if all outputs are zeros or ones. available on ip. outen enable digital outputs (keep low for active outputs) extref disable internal references (keep low for internal references) pd power down (keep low for normal operation) available on ip or with bonding option. v dd power pins for on chip power v ss ground pins ov dd power pins for output drivers table 3. pin functions pin assignment NAD1020-18 28 pin ssop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 bit9 bit8 bit7 bit6 bit5 ov dd ov dd v ss v ss bit4 bit3 bit2 bit1 bit0 28 27 26 25 24 23 22 21 20 19 18 17 16 15 vcm bias1 refn refp bias0 clock outen inp inn v dd v ss extref v dd v ss figure 2. pin assignment for the 28 pin package used for samples
product specification NAD1020-18 10 bit 20 msps sampling adc ip main office: nordic vlsi asa - vestre rosten 81, n-7075 tiller, norway - phone +4772898900 - fax +4772898989 revision: 3.0 page 6 of 11 august 31 st 2001 ip block layout refp refn bias1 bias0 extref vcm inp inn clock or bit9 : bit0 avss avdd avss avdd vdd x y avss avdd avss avdd figure 3. size and pin placement for NAD1020-18. the height and width of the layout is x =1208 m m and y=711 m m respectively in the 0.18 m m cmos process. timing diagram figure 4. timing diagram data clock s a mn-1 p l e s a mn+1 p l e s a mn p l e data n data n-1 data n+1 t d t ap s a mn+2 p l e t h
product specification NAD1020-18 10 bit 20 msps sampling adc ip main office: nordic vlsi asa - vestre rosten 81, n-7075 tiller, norway - phone +4772898900 - fax +4772898989 revision: 3.0 page 7 of 11 august 31 st 2001 input signal range figure 5. definition of full scale range definitions data sheet status objective product specification this datasheet contains target specifications for product development. preliminary product specification this datasheet contains preliminary data; supplementary data may be published from nordic vlsi asa later. product specification this datasheet contains final product specifications. limiting values stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the specifications sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the specification. table 4. definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. nordic vlsi asa customers using or selling these products for use in such applications do so at their own risk and agree fully indemnify nordic vlsi asa for any damages resulting from such improper use or sale. v refp v refn v cm v inp v inn v inp -v inn v rr +v rr -v rr v fsr
product specification NAD1020-18 10 bit 20 msps sampling adc ip main office: nordic vlsi asa - vestre rosten 81, n-7075 tiller, norway - phone +4772898900 - fax +4772898989 revision: 3.0 page 8 of 11 august 31 st 2001 application information references the NAD1020-18 has a differential analog input. the input range is determined by the voltages v refp and v refn applied to reference pins refp and refn respectively, and is equal to (v refp -v refn ). externally generated reference voltages connected to refp and refn should be symmetrical around 0.9v. the input range can be defined between 0.5v and 0.75v. the references should be bypassed as close to the converter pins as possible using 100nf capacitors in parallel with smaller capacitors (e.g. 1nf) (to ground). analog input the input of the NAD1020-18 can be configured in various ways - dependent upon whether a single ended or differential, ac- or dc-coupled input is wanted. ac-coupled input is most conveniently implemented using a transformer with a center tapped secondary winding. the center tap is connected to the cm-node, as shown in figure 6. in order to obtain low distortion, it is important that the selected transformer does not exhibit core saturation at full-scale. excellent results are obtained with the mini circuits t1-6t or t1-1t. proper termination of the input is important for input signal purity. a small capacitor across the inputs attenuates kickback-noise from the sample and hold. series resistors as shown in figure 6 may be advantageous to improve linearity. the vcm-node should be bypassed to ground as closed to the converter pin as possible using 100nf capacitors in parallel with a small one. inp inn vcm mini circuits t1-6t v in adc 51 w 50 w 50 w 22pf figure 6. example of ac coupled input using transformer configuration if a dc-coupled single ended input is wanted, a solution based on operational amplifiers - as shown in figure 7, is usually preferred. the ad826 is suggested for low distortion and video bandwidth. lower cost operational amplifiers may be used if the demands are less strict. a good alternative for high performance applications is to use ad8138 single ended to differential amplifier.
product specification NAD1020-18 10 bit 20 msps sampling adc ip main office: nordic vlsi asa - vestre rosten 81, n-7075 tiller, norway - phone +4772898900 - fax +4772898989 revision: 3.0 page 9 of 11 august 31 st 2001 ad826 ad826 51 w 51 w 470 w 470 w 100 w 100 w 470 w 470 w ad826 51 w in p in n 51 w 470 w input offset video in adc 15pf figure 7. dc-coupled single ended to differential conversion (power supplies and bypassing not shown) clock in order to preserve accuracy at high input frequency, it is important that the clock has low jitter and steep edges. rise/fall times should be kept shorter than 2ns whenever possible. overshoot should be avoided. low jitter is especially important when converting high frequency input signals. jitter causes the noise floor to rise proportionally to input signal frequency. jitter may be caused by crosstalk on the pcb. it is therefore recommended that the clock trace on the pcb is made as short as possible. digital outputs the digital output data appears in offset binary code at cmos logic levels. full-scale negative input results in output code 000...0. full-scale positive input results in output code 111...1. output data are available 6 clock cycles after the data are sampled. the analog input is sampled one aperture delay (t ap ) after the high to low clock transition. output data should be sampled as shown in the timing diagram. pcb layout and decoupling a well designed pcb is necessary to get good spectral purity from any high performance adc. a multilayer pcb with a solid ground plane is recommended for optimum performance. if the system has a split analog and digital ground plane, it is recommended that all ground pins on the adc are connected to the analog ground plane. it is our experience that this gives the best performance. the power supply pins should be bypassed using 100nf surface mounted capacitors as close to the package pins as possible. analog and digital supply pins should be separately filtered.
product specification NAD1020-18 10 bit 20 msps sampling adc ip main office: nordic vlsi asa - vestre rosten 81, n-7075 tiller, norway - phone +4772898900 - fax +4772898989 revision: 3.0 page 10 of 11 august 31 st 2001 dynamic testing careful testing using high quality instrumentation is necessary to achieve accurate test results on high speed a/d-converters. it is important that the clock source and signal source has low jitter. a spectrally pure, low noise rf signal generator - such as the hp8662a or hp8644b is recommended for the test signal. low pass filtering or band pass filtering of the input signal is usually necessary to obtain the required spectral purity (sfdr > 75db). the clock signal can be obtained from either a crystal oscillator or a low-jitter pulse generator. alternatively, a low-jitter rf-generator can be used as a clock source. at nordic vlsi, the marconi instruments 2041a is used. the sinewave clock must then be applied to an ultra high-speed comparator (e.g. ad9696) and a ttl to cmos level shifter (e.g. 74lv04) before application to the converter. the most consistent results are obtained if the clock signal is phase locked to the input signal. phase locking allows testing without windowing of output data. a logic analyzer with deep memory - such as the hp16500-series, is recommended for test data acquisition. power down mode and sleep mode the NAD1020-18 has both power down mode and sleep mode. the power down mode can be used when the adc should be put to zero current consumption state and when a somewhat longer startup time is allowed. the sleep mode can be used to put the adc in an idle state and when the application require a quick startup. the two different power consumption saving schemes can be activated through the pd, bias0 and bias1 pins/connections in the following manner: power down mode: pd=1, bias0=0, bias1=0 sleep mode: pd=0, bias0=0, bias1=0 the actual startup time from these modes are dependent on the external decopling configuration.
product specification NAD1020-18 10 bit 20 msps sampling adc ip main office: nordic vlsi asa - vestre rosten 81, n-7075 tiller, norway - phone +4772898900 - fax +4772898989 revision: 3.0 page 11 of 11 august 31 st 2001 design center nordic vlsi asa vestre rosten 81 n-7075 tiller norway telephone: +47 72898900 telefax: +47 72898989 e-mail: for further information regarding our state of the art data converters, please e- mail us at datacon@nvlsi.no. world wide web/internet: visit our site at http://www.nvlsi.no. ordering information type number description price NAD1020-18-ic NAD1020-18 sample in ssop28 package (limited availability) usd 50 NAD1020-18-evb NAD1020-18 evaluation board including characterisation report and user guide usd 300 table 5. ordering information product specification. revision date: august 31 st , 2001 all rights reserved ?. reproduction in whole or in part is prohibited without the prior written permission of the copyright holder. company and product names referred to in this datasheet belong to their respective copyright/trademark holders.

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